While...Loop itteration limit in VHDL

[mus3na]

hello,

iam having a problems in using while .... loop in VHDL. The tools iam currently used is Xilinx Web Pack 6.2i with SP3.

the problems i faced is :

Analyzing Entity <fetch> (Architecture <fetch_circuit>).
ERROR:Xst:1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more.

so, if anybody know how tu set the itteration limit, please let me know and i will be verry thankfull...

the code is;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-------------------------------------------------------------------------------------
entity fetch is
	port ( mem_data_buffer : inout std_logic_vector(7 downto 0);
	data_mem_read, reset, clk : in std_logic;
	instruction_register_1, instruction_register_2 : out std_logic_vector(7 downto 0);
	mem_address_latch : out std_logic_vector(7 downto 0);
                address_mem_write : out std_logic
	);
end fetch;

architecture fetch_circuit of fetch is
constant rst_pc : std_logic_vector(7 downto 0) := "00000000";
signal pc : std_logic_vector(7 downto 0) := "00000000";
begin
   process (clk, reset, data_mem_read)
   variable loop_count : integer range 0 to 25;
   begin
      if clk'event and clk ='1' then
         if reset = '1' then
            pc <= rst_pc;
         else
            mem_address_latch <= pc;
            address_mem_write <= '1';
            while (loop_count < 25) loop
               loop_count := loop_count + 1;
               if data_mem_read = '1' then
                  loop_count := 25;
               else
                  null;
               end if;
            end loop;
         end if;
      end if;
   end process;
end fetch_circuit;

 

[bmcculla]

Rather than use a while loop, which is hard for the synthisizer to handle, build yourself a little counter to do the same thing. For anything that is going to be synthisized into hardware you should only use while loops for things that are eveluated when you synthisize not when its running.

As far as I can tell you are trying to build a timer to wait for your memory access to finish or timeout. What you have here doesn't do that. Everything in the process is going to happen in one clock including the entire while loop - so it isn't actualy timing anything (which is probably why it's confusing the synthisizer). You need another process that is the timer that starts when the memory access begins and does the same thing you are trying to do in your while loop. Your current process just needs to watch the output from that timer finish the memory access.

Hope this helps
Brent