FYI there seems to be a bug in the ISIS setup of the ADCON1 register on the Vref+. It seems that the ADC Vref+ and Vref - bits are interchanged in the sim. Therefore in order to activate Vref+ /RA3, instead of ADCON1,4 being set. U must set ADCON1,5.
Can anyone please independently verify this bug?
The errata spec sheet does not discuss this so it must be an ISIS (7.8 sp2)issue.
Works OK in ISIS version 7.10.... If it was a bug they must have fixed it..... ALL the pic16 work in very much the same way, so I can't see a bug like that lasting more than a month...
T1con.7 =1 shows active gate inversion as in timer gate triggers when c2out is LOW. This should be timer gate triggers when c2out is HIGH. Verified by the virtual oscilloscope in ISIS and a T1con watch variable.
When I do the physical prototype I'll verify what works precisely and whether the data sheet or ISIS is at fault.