winterhunter
New Member
Dear all,
I was looking into connecting an external SRAM to a PIC18.
In order to avoid dedicating 24 pins (8 data + 14 address + 1 write enable + read enable), I'd rather use 3 bus transceivers (74LS245). Also, I would like to use the same pin to control direction (on the 74LS245) and read enable (on the SRAM - I could later extend the same principle to write enable). One could say that I'm building an ancient ancestor of a computer northbridge...
However, to get a correct timing while taking advantage of the fact that the SRAM is faster than the µcontroller, I would need to be able to send the RE signal around 20 ns latter than the direction signal (for reading it could work without the delay, but for writing a precise sequence is needed to ensure data integrity).
To be on the safe side of things, I would need a 30 ns delay on the signal... How do I implement it?
Thanks
Gonzalo
I was looking into connecting an external SRAM to a PIC18.
In order to avoid dedicating 24 pins (8 data + 14 address + 1 write enable + read enable), I'd rather use 3 bus transceivers (74LS245). Also, I would like to use the same pin to control direction (on the 74LS245) and read enable (on the SRAM - I could later extend the same principle to write enable). One could say that I'm building an ancient ancestor of a computer northbridge...
However, to get a correct timing while taking advantage of the fact that the SRAM is faster than the µcontroller, I would need to be able to send the RE signal around 20 ns latter than the direction signal (for reading it could work without the delay, but for writing a precise sequence is needed to ensure data integrity).
To be on the safe side of things, I would need a 30 ns delay on the signal... How do I implement it?
Thanks
Gonzalo
Last edited: