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NoOneYouKnow

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Hey, I was wondering if anyone could give this a quick look-over for me. I'm needing the counter to display 36, then count down one digit for each pulse at 10Hz. Then, at 00, the AND gates will keep it at 00 until the RLD contacts (switch) are closed. Will my circuit work?

**broken link removed**
 
Something is wrong.

The most significant is set up to 0110 = 6, the less is set up to 1100 = 12 (BCD is from 0 to 9, so your counter will start overflowed).
 
GOkussj5okazu, the reset overrides the load enable (RLD), so the circuit will get stuck at zero count.
You don't need the complicated decode for zero count. The carry out just needs to be inverted and gated off by RLD. It also needs to be gated by clock to eliminate glitches in the carry out.
Below is the countdown circuit.
 

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Good suggestion.
 
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Thanks guys, I think I got this figured out. How's this look?

**broken link removed**

Just to make sure;

1. The RLD switch, no matter when pressed, will reset the count to 36, correct?
2. Even if the CLK pulse is stopped, the RLD will still function?
 
The counter looks OK. I didn't check the 4511s.
There is a possibility that once in a blue moon you will get an error due to a race between the clock and the asynchronous falling edge of RLD.
Schematics with traces passing through component symbols make them difficult to read. The practice should generally be avoided.
 
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Sorry about that, I'm just learning my way around Eagle. ^_^ Thanks for all the help though.

Actually, I have one more question. On the RLD button, would it be possible to make that positive-edge triggered? By that I mean, make it to where it will reset once when you initially press the button, but holding the button won't keep it in reset. I know how to edge-trigger a 555, but I wasn't sure if that same method would work with this.
 
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Sorry to double post, but I noticed something. With the NOR gate, the output is what will hold the count at 00 until RLD is pressed correct? This relies on Count Out being low, and CLK being low. But, what if CLK goes high? Won't that cause the NOR output to go low? Sorry, I'm just greatly confused here for some reason.

It makes sense why and how CO and RLD would work, being gated into RS, but I don't understand the need for CLK.
 
In my simulation, Cout* has a short glitch before the count gets to zero, causing the count to jump from 10 to 0. The glitch can be gated out with clock going into the NOR gate. You are correct in saying that reset is pulsed during the time the count is at zero, but due to the propagation delay of the gate, reset stays high during each clock cycle until shortly after the clock goes high, so clock is internally inhibited by reset. Once RLD is asserted, the count jumps to 36, causing Cout* to go high, which causes reset to go low.
 
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