CMOS threshold voltage vs speed and leakage power

Hi all,
I'm reading on CMOS and came across following fact

CMOS with low threshold voltage (lvt) is used in high-speed (time critical) designs but they have higher leakage power consumption
CMOS with high threshold voltage (hvt) is used in low-speed (not time critical) designs but they have lower leakage power consumption

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I was searching through the internet but couldn't find any information explain how low threshold voltage is fast but consume more power and how high threshold voltage is slow but consumes low power.

All the documents I came across simply states "lvt is for fast, and hvt is for slow,low power"

So can somebody please explain how FET with low threshold voltage has higher speed and higher leakage current while FET with high threshold will be slow but low on power?

Thank you very much.

The low and high power consumption applies to static conditions or low frequency operation. Under those conditions the lower leakage current of high threshold devices allows for lower power operation.

For operating at a high digital frequency the low threshold devices use less power since you can operate them at a lower supply voltage, which reduces the power required to charge and discharge the stray circuit capacitances. Also lower threshold devices generally are smaller, faster, and have lower parasitic capacitances, which also lowers dynamic power.

The higher leakage current of low threshold devices is because the threshold becomes so low that the transistor is not completely turned off, so the OFF current becomes significant in large circuits with many transistors, such as microprocessors.

I'm a little skeptical about the statement you quoted. It's a little vague to have any real meaning. You really need to make a comparison based on some real numbers. Also, leakage is almost always measured as current, not power. Granted, power is the product of voltage and current, but if the current is up 10%, while the voltage is 30% lower, the power will be lower. As such, I'd really want to look at the rest of the article your two lines came from before putting a lot of stock in it.

Also, leakage current is usually pretty small compared to switching losses for high frequency logic. So i must ask, what are the actual operating conditions for the comparison?