Display TFT ST7789 (OshonSoft Basic).

DogFlu66 · Jun 7, 2024

I leave the library to use ST7789 TFT display, I have translated one that is in C language. But unfortunately I have not been able to get it to work yet. I leave the files in case someone with more experience with these displays can review it.

camerart · Apr 3, 2025

DogFlu66 said:
There shouldn't be any difference in the microcontrollers because the packaging is different.

I've tested both types of displays with the 46K22 and 46K20, and they worked fine.

Hi D,
Are they surface mount or through the hole PICs?
C.

DogFlu66 · Apr 3, 2025

The seconds.

camerart · Apr 3, 2025

DogFlu66 said:
The seconds.

Hi D,
When you say seconds, does this mean 'through the hole?
C

DogFlu66 · Apr 3, 2025

camerart · Apr 4, 2025

DogFlu66 said:
View attachment 149475

Hi D,
I though so.
My problems could be surface mount 18F46K20s and my PCB combination.
C.

camerart · Apr 4, 2025

DogFlu66 said:
There shouldn't be any difference in the microcontrollers because the packaging is different.

I've tested both types of displays with the 46K22 and 46K20, and they worked fine.

Hi I and D,
As all of my peripherals work (need re-checking) with MODE 2 I'll leave the TFT SPI set like that FOR NOW, until I've clarified it.

Looking at the 18F46K20 errata d/s
Here is one very similar to what I'm getting with the data analyser (CLK error)

Microchip want me to clarify a couple of things, so I'll mention this.

NOTE: I have a lot of difficulty with my analyser using CPOL CPHA and the 1846K20 D/S using CPE CKP. (START MIDDLE and END??)
C

Nigel Goodwin · Apr 4, 2025

camerart said:
Hi D,
I though so.
My problems could be surface mount 18F46K20s and my PCB combination.
C.

There should be no difference, surely it's just the exact same die in a different encapsulation. Any issues are more likely to be errors in the code or in the PCB.

Don't try and do everything all at once, strip the code right back so nothing except the display is there, and get that working first - then gradually add extra parts - checking each time, that the display still works, and that the new sections do.

camerart · Apr 4, 2025

Nigel Goodwin said:
There should be no difference, surely it's just the exact same die in a different encapsulation. Any issues are more likely to be errors in the code or in the PCB.

Don't try and do everything all at once, strip the code right back so nothing except the display is there, and get that working first - then gradually add extra parts - checking each time, that the display still works, and that the new sections do.

Hi N,
I've had strange problems with this PIC for a year or two suspecting, and being advised that it's most likely my fault, but there are SPI errors shown in the D/S for this pick when set a certain way.

I'm going through all of the other possibilities, to report to Microchip as they have asked me to. One is SMD or TTH, and D hasn't had any problems with his TTH PIC, that's all.
C.

Ian Rogers · Apr 4, 2025

When I test SPI on THAT chip there appears to be a "good" clock then it goes messy and then off as if the LCD is shorting the clk pin.. I know its not as I can run the same code on other chips.

As soon as I get chance I'm going to try the pic18f46k42 as the SPI seems to be stand alone.. and can be faster.

camerart · Apr 4, 2025

Ian Rogers said:
When I test SPI on THAT chip there appears to be a "good" clock then it goes messy and then off as if the LCD is shorting the clk pin.. I know its not as I can run the same code on other chips.

As soon as I get chance I'm going to try the pic18f46k42 as the SPI seems to be stand alone.. and can be faster.

Hi I,
At the moment, I'm trying to set my digital analyser to show the SPI clock clearly when not showing set-up errors. I have problem between CPOL CPHA and CKE CKP. (This is just to explain not for suggestions) I have a discussion on AAC at the moment. (It's just me I'm afraid)

Once I get a good SPI CLK, which indicates just what you are saying, I'll post it along with answer to a couple of Microchips clarification questions.

I'm pretty sure that the SMD 18F46K20 has SPI problems, perhaps with particular batches, or TTH or whatever.
C.

DogFlu66 · Sunday at 6:10 AM

Ian Rogers said:
When I test SPI on THAT chip there appears to be a "good" clock then it goes messy and then off as if the LCD is shorting the clk pin.. I know its not as I can run the same code on other chips.

As soon as I get chance I'm going to try the pic18f46k42 as the SPI seems to be stand alone.. and can be faster.

I’ve been comparing the clock (CLK) waveforms of the SPI bus between the PIC18F46K20 and the PIC18F46K22 microcontrollers, and I’ve observed that the 46K22 maintains a much cleaner and more stable waveform than the 46K20. This could be due to internal differences in chip design, switching characteristics, or improvements in output drivers.

On another note, regarding the type of package used, in theory, the DIP (Dual In-line Package) tends to have poorer electrical performance compared to SMD (Surface Mount Device) packages. This is mainly because DIP packages feature longer pins and trace lengths, which can increase parasitic inductance and capacitance, making the circuit more prone to external electromagnetic noise. These factors can significantly impact signal integrity, especially in high-speed or high-frequency applications such as SPI communication.

camerart · Sunday at 7:17 AM

DogFlu66 said:
I’ve been comparing the clock (CLK) waveforms of the SPI bus between the PIC18F46K20 and the PIC18F46K22 microcontrollers, and I’ve observed that the 46K22 maintains a much cleaner and more stable waveform than the 46K20. This could be due to internal differences in chip design, switching characteristics, or improvements in output drivers.

On another note, regarding the type of package used, in theory, the DIP (Dual In-line Package) tends to have poorer electrical performance compared to SMD (Surface Mount Device) packages. This is mainly because DIP packages feature longer pins and trace lengths, which can increase parasitic inductance and capacitance, making the circuit more prone to external electromagnetic noise. These factors can significantly impact signal integrity, especially in high-speed or high-frequency applications such as SPI communication.

Hi D and I,
This backs up our anecdotal findings of our different 18F46K20 set-ups.
I'm just about to reply to Microchip, with their questions, so I can add this into the message.
Can you clarify or show different results please, then I can add them into the message?

As for your TTH pic working better than our SMD pics, perhaps the stray capacitance helps?

I don't have the skills or equipment to test properly.
C.

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