Logic circuit for two cameras and one flash.

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Ok, I found some ESD information for this part in this document: https://www.electro-tech-online.com/custompdfs/2007/12/szza036b.pdf With an additional series 1k resistor on the input lines, the internal clamp diodes should be good enough protection.

"The TI logic families with clamp diodes in the inputs are: AC, ACT, AHC, AHCT, ALB, ALS, ALVC, AS, F, (CD)FCT, HC, HCT, HSTL, LS, PCA, PCF, S, SSTL, and TTL. The TI logic families without clamp diodes in the inputs are: ABT, ABTE, ALS, ALVT, AUC, AVC, BCT, FB, GTLP, GTL, LS, LV, LVC, LVCZ, LVT, (CY)FCT, SSTV, and VME."
 
CMOS ICs have internal protection. But they still need careful handling as the protection is not 100%.

Have you looked at the data sheet for the 74HC73?

What are the limits (if any) on the clock rise and fall times?

I notice that you have 1M pull up resistor on the Clk inputs.

This will result in a slow rise time if the camera outputs are open collector types.
 
Ok, thanks. It probably is best to allow for a little capacitance in the input lines. I decreased the input line pull up resistors to 100k, and added series 1k resistors for ESD protection. The cameras use SCR's to trip the flashs, so they would be open collector type. Here is (I hope) the final version.
 

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I just looked at the data sheet for the 74HC73. It is a good choice for your circuit since it has Schmitt Triggers on the clock inputs. Thus it is not sensitive to the clk rise and fall times.

But 100k is a better choice anyway.
 
ljcox said:
You need a 100 nF ceramic capacitor between pins 8 & 16 of the 74HC109 to act as a bypass. It will NOT work properly without this cap.

Howdy,

I know my point here is a side issue, so I hope to not detract too much, but I must say I am surprised to hear you say this. Decoupling is important, but to say this level is required or it will not work? 100nF at that chip or it will not work? I've not seen this.

National's HC design guide (AN-375), for example, suggests 10nF per every two to five packages (spaced within 12cm), and 100nF for every ten.

Just curious...
Corey
 
I meant that it won't work without decoupling.

The National "FACT" book suggests 47nF. So as a rule of thumb, I use 100 nF per 2 ICs.
 
ljcox said:
I meant that it won't work without decoupling.

The National "FACT" book suggests 47nF. So as a rule of thumb, I use 100 nF per 2 ICs.

Okay to the first part.

But you're applying FACT guidelines to HC parts? They're different families with different requirements...

thanks,
Corey
 
saturn1bguy said:
Okay to the first part.

But you're applying FACT guidelines to HC parts? They're different families with different requirements...

thanks,
Corey
I know, but does it matter?

There is no difference between a 10 nF and a 100 nF in the price or size.

In my opinion, the more bypassing capacitance the better.
 
ljcox said:
I know, but does it matter? There is no difference between a 10 nF and a 100 nF in the price or size. In my opinion, the more bypassing capacitance the better.

The only thing I ever took objection to was:

ljcox said:
You need a 100 nF ceramic capacitor between pins 8 & 16 of the 74HC109 to act as a bypass. It will NOT work properly without this cap.

Which is false.

(My objection was about propagating proper design principle instead of applying a generalization that isn't correct. Your solution will work, certainly, but that's not what I objected to: 1) If the user already has proper bypassing in his power supply and the chip is located nearby he doesn't need it, 2) Even if he doesn't have proper supply bypassing, if he has 10nF within 12cm of the HC109 he will be alright, 3) In no circumstance does he require a bypass cap at the power terminals of an HC part.

I'm afraid I've detracted from the issue at hand already, alas. This was not my intention. Everything else you've said is great and I've enjoyed reading it.)

thanks
Corey
 
I think "false" is a bit strong.

Yes, I agree that he does not need a bypass if there is at least 10nF in his power supply and it is within 12 cm of the IC. But, I don't know what type of power supply he has or if it is further than 12 cm from the IC.

My concern is that if he built it without any bypass cap. and the PS bypass was inadequate or too far away, the circuit could behave strangely, ie. not work properly and he could waste time trying to find out why.

He may even be using a battery. If so, its internal resistance will increase with age - thus causing the circuit to fail prematurely.

I had not seen the AN that you mentioned, so thanks for mentioning it.
 
ljcox said:
My concern is that if he built it without any bypass cap. and the PS bypass was inadequate or too far away, the circuit could behave strangely, ie. not work properly and he could waste time trying to find out why.

Now that's worded beautifully! I couldn' agree more
 
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