Get rid of E1. Put B2 in its place, with V=delay(v(GTDR),5u). But this is only a kludge and will not give true interleaved PFC, because the 1249 oscillator frequency/pulse-width are not constant.
GTDR is running at about 30Khz. Period 33.2us, Pulse width about 4.3us. I believe each mosfet should alternately trigger on the leading edge of each GTDR output pulse (not on the same output pulse) which means each will operate at half of the frequency of GTDR. So if you really want this to run at 100khz , the operating frequency needs to be higher.
Ok, but although the PFC is now 'interleaved' (after a fashion), both FETS trigger on each GTDR pulse rather than on alternate pulses as etech mentions in post #84. I don't know enough about PFC to say if that's adequate, but perhaps it's ok with your supervisor?
Ok, but although the PFC is now 'interleaved' (after a fashion), both FETS trigger on each GTDR pulse rather than on alternate pulses as etech mentions in post #84. I don't know enough about PFC to say if that's adequate, but perhaps it's ok with your supervisor?
Yes. A flip-flop can give you alternate pulses. In LTspice you have the srflop, That could be used in conjunction with AND gates to steer gate-drive pulses. The output voltage of logic gates can be set to, say, 10V for driving MOSFET gates.
Hmm, how can the logic control look like alec_t? Not sure where to implement 10 V. Fundamental logic gates is not my strongest subject :/ sorry about that.
--edit--
I mean the logic gates look different here in LTspice I think. I found this demo, that could help a bit.
Yes. A flip-flop can give you alternate pulses. In LTspice you have the srflop, That could be used in conjunction with AND gates to steer gate-drive pulses. The output voltage of logic gates can be set to, say, 10V for driving MOSFET gates.
I think that if you want each mosfet to get alternate pulses, then a D-flipflop, set up as a divide by 2 would work better. Then separately AND Q and Q-not with GTDR to feed the two mosfets.
I think that if you want each mosfet to get alternate pulses, then a D-flipflop, set up as a divide by 2 would work better. Then separately AND Q and Q-not with GTDR to feed the two mosfets.
Chris, and alec_t, what do you mean divided by two? I have attached the file once more, so you can see the connection. I may have misunderstood something.
The D-flipflop does not itself provide dead-time (the interval needed between one MOSFET switching off and the other MOSFET switching on). The 10nS parameter you referred to is the response time of the flipflop.
You make divide by 2 with a D-flipflop by feeding it's D input from it's own Q-not output.
Feed the GTDR to the CLK pin of the D-flipflop. Q and Q-not goes to one input of two AND gates. GTDR goes to the other input of the AND gates. The outputs of the two AND gates drives the mosfets.
No dead time is needed on the output of the flipflop, because we are ANDing it's output with the original gate pulse. (*) This will maintain the same modulated pulse width, but it's now alternately directed to the two mosfets.
* Assuming that the duty cycle never approaches 100%
Thank you guys, it seems to work now, thanks to your instructions. My only concern is that the current input waveform have spikes, it should be more sinusoidal with the voltage waveform I think. But maybe it is still okay.
My only concern is that the current input waveform have spikes, it should be more sinusoidal with the voltage waveform I think. But maybe it is still okay.