Reply to FRED6298
>Did you check the 5V for the u-controller ? From the schematic, the >Zener is in backwards. Maybe a typo.....??
Ans: Yes, it is a typo. Thanks. Since, I have check the 5V, which is relatively stable.
>You say that you are generating a 'sine' - wave output from the 89C51.
>The 89C51 has digital ports. ......??
Ans: Actually, the "sine" I am referring is the PWM signal (which is a train of digital pulse from the 89C51), "sine" means that the pulse width of the PWM signal is proportional to the magnitude of the signa wave.
>1. From some of the 'applications', a cap ~ 2.2uF is connected from Vs >to LO. I expect that the 'sink' FETS need a boost voltage as well as >the 'source' FETS.
Sorry to say that I don't agree with your comment. Since the NMOS Vth is around 2-5V and the maximun voltage ta the LO port is Vdd (which is 12V in my design). So, no boosting is needed.
>2. I noticed that there are no decoupling capacitors on the IRF2110 12V >to ground. Ditto that on the 89C51.
Yes, I just want to save some time, even my PCB already resevred the de-coupling cap. slot. In my mind, may be I should do it to eliminate the unknow.
>Remove the load on the secondary. Remove the PWM signals from the u->controller.
>Simulate the inputs with a reistor pull-up to 5V and a resistor pull-down >to ground. Result ...> this should lock the IR2110's into a half-bridge >mode. Check the loop = Source FET from 12V to XMFR primary to sink >FET to ground. Both FETS = ON and conducting.
>Reverse the inputs, then Repeat for the remaing two FETS.
>If O.K., return the inputs to the u-controller, And see what happens(No ->Load)
Ans: Actually, it is very dangerous, since there is a leakage inductance in the transformer. If I apply such biasing condition, the current will keep increasing until they reach the maximun limit of the mosfet. Any comment on my statement? Thx
>Do you have an oscilloscope ?
Ans: Yes
Thanks alot Fred
P.S. Attached is the updated schematic with the correction on the diode direction.