Since this thread has diverged from the original question, I've changed the title. Hope this doesn't make things confusing.
Here's an update of the circuit after tonight's festivities. The diagram now includes the blocking oscillator that's used as a frequency divider, and the JK flip-flop.
I wish everything worked as well as the blocking oscillator. Its pulse width is set by the transformer characteristics, and the repetition rate by the RC network. By adjusting its RC timing network values, it will divide the crystal oscillator by all kinds of different values, including non-integer values. I have it adjusted to divide by 3.5 at the moment, so that it produces 10.857142 kHz from the 38 kHz reference, which is close to the 10 kHz frequency that I'll eventually be working with. The transformer is one that I removed from a dead switching power supply. I don't know much about it except that primary and secondary inductance are both 20 mH, and turns ratio is 1:1.
The flip-flop is now working, but it was a bit tricky:
- The -100V grid bias is fairly critical. I found that if it varies by more than ±5V, it stops working.
- The blocking oscillator puts out a very good negative going pulse with very fast leading edge which is ideal, but I found that the pulse duration was too short to trigger the flip-flop. So I added the pulse stretcher. This still gives the fast leading edge, but lengthens the pulse enough that the flip-flop switches reliably.
The J & K inputs appear to work, but more testing will be necessary. I'm concerned that their setup time may be too slow. The flip-flop will be used to sample and hold the output of the VCO (yet to be designed), and so the J & K inputs will have to react quickly.