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I wonder if the author tried to email Roman to ask for clarification before publishing the article?
Thanks for looking out for me Mike and I appreciate you bringing it to my (and everyone's) attention.
No Colin did not contact me for permission or clarification before posting his criticism, however he did have the courtesy to email me afterward saying he had done a critique, and he has met my copyright requirements by posting a link back to my original web page.
I had a bit of a chuckle at his critique as I feel it showed some lack of understanding on his part.
I had just chosen to ignore it, believing my description was fairly accurate and easy to understand.
I'll comment now on his comments;
Phase1; ON
"thin purple arrow is vague". I labelled this as "base current path". This shows the base current from Q1 is not wasted, the base current finds its way to the load.
"yellow arrow is a mystery". It's not a mystery I called it "regulator current path" and true to its name all the current used by the Q2 regulator transistor also finds its way to the load.
Phase2; TURN OFF
"The arrows above are vague and misleading and incorrect".
I think here that Colin shows an ignorance that the "turning off" phase is different to the steady-state "off" phase and/or a total understanding of what I was saying.
The turning off phase involves the discharge of caps. As the buck turns off the inductor pin point A slams below 0v, this causes C1 to discharge and the +ve voltage in C1 to cause a current through C2, as shown by my blue arrow. This current is obviously blocked by the diode, so its path must be through L1 and hence to the load.
All current through RZ cannot be conducted through the zener as point Z is now below the zener voltage, so RZ current likewise contributes to load current (my thin purple arrow).
Phase 2A (colin just made 2A up and scribbled on my diagram)
Here he has said some of the same things i have said above, but in a different way. He still has some misunderstanding of the turn off process;
"At the same time it charges C2 and C1 is discharged slightly". No. C2 is charged slowly during the "off" phase which we talk about next. The "turn off" phase is a transitory phase where C1 energy is dumped through C2 causing the voltage on point Z to drop sharply as C1 energy is dumped through to the load.
This can be seen here on the voltage on point Z (the sharp drop from 5.6v to 3.0v);
**broken link removed**
Obviously that voltage can only drop if energy is dumped out of C1. My diagram for phase2 explains where it goes.
Phase3; OFF (delay period)
"I don't know what is trying to be explained in Phase 3. I don't know what the author means by "Delay Period"... Yep that sums it up. I clearly explained the action of the "off" phase and the delay on my webpage. Maybe Colin did not read it?
It is common in SMPS buck ICs to use a "timed off" period, usually a monostable. I managed to mimic this effect by the combination of C1 and C2 and the energy dump as explained in Phase2. Once C1 has dumped and is at 3v, there is a clearly defined "delay period" while C1 charges again (via RZ) and during this delay period the buck Q1 remains off. This gives a big drop in frequency and improves efficiency for a number of reasons, and also greatly increases stability.
This is also the main difference between my 2tran regulator and Richard Ottosen's original 2tran oscillating regulator. His regulator simply oscillated around a regulating voltage, and was very dependant on load conditions, and was lower in efficiency due to slow switching times and higher frequency.
My regulator provided the "fixed off-time delay period" as used in good buck designs, so it triggers OFF at the regulated output voltage, then has a fixed delay before it can trigger back on. So my design is able to achieve similar performance to a digitally switched Buck SMPS IC as it mimics the very fast switchign times AND the vital "fixed off-time delay period".
I think Colin might not be as familiar with modern Buck designs and had missed this important point entirely.
"C1 is not charged by Rz". C1 is entirely charged by RZ during the "off" phase, unless Colin thinks it is being charged by current out of the base of Q2!!
"and C2 charge-path is not as shown in the diagram above." C2 charge is exacly as I have shown it. As the voltage on C1 rises (due to current through RZ) the voltage on the left pin of C2 must also rise, so RZ supplies current to charge both C1 and C2 during the nice ramp as shown in the 'scope photo above. For C2 to charge during this time, there must be current through C2 which for the reasons I mentioned above current through C2 goes to the load. My diagram is correct.
Phase4 TURN ON
"As you can see, arrows on a diagram are misleading and meaningless." Rather than correct all of Colin's description of this phase, it seems he has an incomplete understanding. The "turn on" is not initiated by a drop in the output as with a setpoint type regulator, because of that critical "delay period" I mentioned the turn on will occur after the delay period when C1 has charged high enough to turn on Q2.
"At the same time C2 charge C1." Correct, but Colin does not understand so is my blue arrow which shows current through C2 into C1 must come through Q1. Also the current surge through C2 causes a higher current pulse into the base of Q2, which can be seen on my 'scope waveform as a "blip" where Q2 base voltage is higher for a short period.
"The yellow base-current path does not pass through R1 but the emitter-base junction of Q1." Finally, a correct critique from Colin. The yellow arrow I correctly called "base current path" but my diagram shows it through R1. In reality with my tested values of R1=1k2 and R2=2k7 there is about 8.4v on R2 =3mA, and 0.6v on R1 = 0.5mA so the "base current path" is 2.5mA from Q1 base and 0.5mA through R1. From memory I called it correctly "base current path" but on the diagram I likely drew the arrow beside R1 to make it less messy. If you check my diagram for Phase1 I drew the base current arrow between R1 and Q1 (as a simplifaction) to show the current really passes through both parts.
"The author did not have an understanding of the operation of the circuit and this confused me greatly." I have no trouble believing that Colin was "confused greatly", but as for me not understanding the operation of my circuit I have hopefully cleared that up in this post.
I'm not exactly sure why Colin wanted to critique my design while barely understanding it, I don't think it really adds to his web page and it does not really affect my web page or the large number of people who have used, understood and tuned my circuit and gained a benefit from it. At this point I think it's some attampt by Colin to add new content to his own page with very little effort on his part and maybe provide cross linking of our two web pages to increase his web traffic. I have not asked him to take down his faulty critique, it does not effect me much and if anything just makes him look bad.