Uni Project Advice and Help

[Nopse]

I need to do the following for a project at uni:
Fixed frequency divider by 33. The counter used will have the synchronous R input. Only circuits will be used
from the HCT/HC series. The oscillator will provide two rectangular signals with frequencies of 5Hz and 435kHz respectively
and a manual clock signal.

This is what I've done so far. Everything in the left side of switch 3 is mandatory. I'm new to Proteus. The simulation doesn't work, not even the first led lights up. Can someone help or give some advice please?

 

[AnalogKid]

Things are so scrunched in there that it is hard to read. If the cap is being charged and discharged through the same 1 K resistor, why are charge and discharge at two different rates? Wouldn't that take 1 diode and 2 resistors?

ak

 

[Tony Stewart]

Each narrow pulse has a target of Vcc. When V(reset) reaches Vcc/2 it activates master reset . Then the decay slew rate is 1/2 because the target voltage ΔV is 1/2 decaying from Vcc/2 to 0V so the decay slope is half.
dV/dt = ΔV/RC

 

[AnalogKid]

Not what I was asking about. In your schematic, it *appears* that the cap (reference designators - !) is charged through the resistor for a fixed amount of time, then discharged through the *same* resistor for the *same* period of time. Yet your sim shows that the charge slope is steeper than the discharge slope. Please expand that portion of the schematic for clarity.

BTW, there used to be a television electronics company named Richmond Hill in Richmond Hill. Installed their gear in the 70's.

ak