Diode Drop Accuracy

[ronsimpson]

Microchip say 10k max at the voltage of interest.

The impedance at the ADC input is about 10k. (100k||9.31k)+1k Thats 100k parallel with 9k then add 1K. MicroChip is not talking about the resistance to the voltage source but the impedance. (from the ADC's point of view it looks like a 10k to 8.3 volts)

Inside the ADC there are input protection diodes. (to ground and to supply) There diodes can only take a small amount of current.
The diode on the outside limits the voltage to -0.7V. The internal diode limits the voltage to -0.3V. That puts 0.4 volts across the 1k resistor or 400uA.
The same story on the supply side.
edited----
Impedance:
Your scope has a input impedance of 1meg. Add a 10:1 probe with a 9meg resistor and the tip of the probe has a impedance of 10meg and a output of 1meg.

 

[Pommie]

If you are trying to detect zero crossing then both circuits need to work at the same time. Is this what you are trying to do?

Mike.

 

[rjenkinsgb]

The impedance seen by the ADC pin equivalent of paralleling the two resistors used in the divider.
It's under 10K.

Edit - didn't see Rons post above, ignore me..

 

[ACharnley]

I'm still confused how 100k = 10k. The ADC works by sampling, a cap charges and is disconnected. At lower voltages the 100k charges it too slowly and gives an invalid reading.

Mike - controlling two FET drivers either side of a bridge (active rectification) so need to know which side is positive.

 

[dknguyen]

I'm still confused how 100k = 10k. The ADC works by sampling, a cap charges and is disconnected. At lower voltages the 100k charges it too slowly and gives an invalid reading.

Mike - controlling two FET drivers either side of a bridge (active rectification) so need to know which side is positive.

I believe he's referring to the AC analysis where you "turn off" all DC sources which means all voltage sources become 0V (short-circuits) and all current sources become zero current (open circuit). Thus, the +V becomes 0V and the high and low resistors in the divider end up being in parallel.

You two are talking about two different things/concerns. I'm not sure that I completely Ron on this one because your signal source is AC so does not get "turned off" in the analysis.

 

[Pommie]

The input impedance is a maximum value. If it is too high then it takes longer to charge the sample and hold capacitor in the pic. If you leave the ADC channel open then the S&H cap will track the voltage. Your problem is reading two samples at the same time.

Mike.

 

[ACharnley]

Hi Pommie, that is correct.

Another option (the only one that I can see) is to take the DC reading (which gets rid of the diode) and use the diode on another pin to detect the side. It'll trigger at 0.7v but being able to work out the frequency it should be possible to derive when the actual zero crossing is.

These readings are to prevent backflow so perhaps I'll just turn the FET's on at +1v over the storage voltage.

 

[ronsimpson]

I'm still confused how 100k = 10k.

Put a ohm meter from ADC input to ground and you will measure near 10k. This is the impedance as seen by the ADC.

 

[ACharnley]

Ok I see where you're going with this but the 100k is key here not impedance to ground. As Pommie described the PIC ADC uses sample and hold so the 100k isn't going to cut it.

 

[schmitt trigger]

The source impedance as seen by the ADC is the Theavenin equivalent, in other words, the parallel of 100k and 9.31k = 8.51k.

 

[ronsimpson]

100k is key here not impedance to ground.

Disagree.
If you add a capacitor from ADC input to ground, the time constant is (C and 10k) not (C and 100k).

 

[OBW0549]

Ok I see where you're going with this but the 100k is key here not impedance to ground. As Pommie described the PIC ADC uses sample and hold so the 100k isn't going to cut it.

WRONG. What the others have been telling you is correct.

 

[Pommie]

Why don't both lines cross zero at the same time. If they don't then isn't the ground reference wrong?

Mike.
BTW, a cap on the adc input can act as a very good reservoir for the S&H cap.

 

[ACharnley]

WRONG. What the others have been telling you is correct.

I still don't get it. The 100k is restricting the current into the ADC. By too much. What am I missing?

 

[ACharnley]

I've increased the PIC pin count and separated the voltage monitoring (for zero cross) and polarity detection into two functions.

 

[Pommie]

You're not measuring the line voltage but the voltage after the divider, so 10k impedance.

Can you answer my question why the two phases don't cross zero at the same time?

Mike.

 

[ACharnley]

Hi Mike, I don't recall saying they didn't?

OK so the ADC sees 10k to ground, but the 100k is still restricting the current too much. This is the part I don't understand.

 

[ronsimpson]

OK so the ADC sees 10k to ground, but the 100k is still restricting the current too much. This is the part I don't understand.

The 100k has 100 volts across it while the 10k has 10 volts across it. (assuming a simple divider and using rough numbers. (same current) So 100k and 100V pushes into the ADC in the same way that 10k and 10V does. (that is a strange way to look at it and certainly not how I teach electronics)

A different way to look at it: If we put a 0.1uf capacitor on the output of the divider, it will roll off the high frequencies. The frequency response will be (cap & 10k) not (cap & 100k). If you have SPICE you can test that.

A different way to look at it-2. Voltage divider; now take the bottom resistor down to 0 ohms. (what is the impedance of the output?) (hint the 100k has no effect at all in this case)

 

[schmitt trigger]

Hi Mike, I don't recall saying they didn't?

OK so the ADC sees 10k to ground, but the 100k is still restricting the current too much. This is the part I don't understand.

What you are missing is basic electrical theory.
Several posts ago I told you it is the Theavenin equivalent. Google it.

 

[OBW0549]

I still don't get it. The 100k is restricting the current into the ADC. By too much. What am I missing?

What you're missing is exactly what schmitt trigger said: basic circuit theory. Specifically, the fact that from the ADC's point of view, the 100K and the 10K are in parallel and that it is the resulting parallel impedance-- and NOT just the 100K resistance-- that will determine the ADC sampling time needed as well as any static errors due to the I*R drops due to the ADC's input leakage current.

Stop distracting and confusing yourself with informal, intuitive stuff like "the 100k is restricting the current into the ADC" and stick rigorously to circuit theory. Intuition can be useful, but ONLY when grounded in a solid understanding of circuit principles.