Diode Drop Accuracy

[ACharnley]

Clearly I'm missing a trick here.

Say the input is +100V relative to ground. At a 100/10 ratio 10V is at the divide, partially shunted to 3.3v by the zener. The current which charges the cap is restricted by the 100K resistor.

Say the input is -100V relative to ground. Current flows through the bottom diodes through the 100k. There is also a pull on the PIC's pin.

 

[ronsimpson]

The current which charges the cap is restricted by the 100K resistor.

100V and 100k ohms = 1mA. So the capacitors inside the ADC could charge at 1mA rate. Up to 10 volts because of the divider. .
10V and 10k ohms = 1mA. So the capacitors inside the ADC could charge at 1mA rate. Up do 10 volts.
The ADC can not see any difference between two circuits. (100 volts driving a 100k & 10k divider or 10k to 10 volts)

On the negative side: assuming the diodes you are talking about are the input protection diodes; The -100V and 100k = 1mA and is just the same as -10V and 10k = 1mA. The input diodes will see the same current.
----edited----
Have you looked at the max current for the input protection diodes?

 

[ACharnley]

I'm determined to understand this.

First sentence -understood.

Second sentence - this 10k comes from where?

 

[ronsimpson]

this 10k comes from where?

The voltage divider, bottom resistor is about 10k. (actually it is both resistors in parallel)

You understand that a ohm meter at the ADC input measures all resistors. It is easy to see the resistors going to ground. The 100k is not left open but connects to a signal source that is very strong. When that source is at 0 volts (zero crossing for a AC signal) the 100k looks like it is connected to ground. When the signal is at -100 or 0 or +100 it is a strong source. From the ADC's point of view it see the 9.31K is connected to a strong point and the 100k is also connected to a strong point. When the ADC needs to charge its capacitors it pulls and pushes on the outside world. It sees the 100k and the 9.31k connected to a very stiff point that can't be moved. Thus the 100k seems to be in parallel with the 9.31k.

Maybe you are looking at the circuit from where you stand and thinking volts. Try standing inside the ADC and thinking about measuring resistance and impedance. From inside the ADC if you try to lift the pin in voltage the resistors will try to bring the voltage back to where it belongs.
Example: Input=25V. 10:1 divider. Input to ADC=2.5V. From inside the ADC all methods of measuring will see 10k to 2.5V. (I know 100k parallel with 9.31k does not equal 10k but approximately) From the ADC point of view it can not tell if there is a voltage divider from a large signal source or a 10k to 2.5 volts. (we can do the math if you want)

Another way to think about it:
100V 100k resistor and the 10k to ground. (voltage divider 10:1 like we have been talking about)
Add a large capacitor from output of the divider to ground.
The output is 10 volts with the capacitor charged up.
Now bring the 100 volts down to 0 volts and watch the capacitor discharge. The discharge current flows through the 10k to ground an through the 100k to ground or 0V. So the capacitor will discharge at a time of C and 9k which is 100k in parallel with 10k. It is easy to see the capacitor will discharge at about the 10k rate not the 100k rate.
The capacitor charge rate is also 10k fast not 100k slow but that is harder to see.

From the ADC point of view and from the capacitor's point of view the output of a voltage divider is low not high resistance.

 

[Pommie]

Hi Mike, I don't recall saying they didn't?

I'm confused. Why do you need to monitor both lines. They cross zero together ano when one is high the other is low so what purpose does the second circuit serve?

Mike.

 

[ronsimpson]

Why do you need to monitor both lines.

I do not know why but likely the 100 volt supply has a return line that is not quite at ground.
Example: In the US the 110Vac has a return line that is near but not at ground. I have seen 10 volts on neutral. If the computer is at earth ground and neither power line is at earth ground there will be this problem.

It might be wise to use a differential amplifier to look at L1 and L2. The voltage of Line1 - Line2 will be referenced to the computer's ground. Or the amplifiers output could be referenced to 1/2 the supply voltage. This allows the computer to see zero crossing.

 

[Pommie]

Post #37 seems to suggest that the two lines do cross at the same time.

Mike.

 

[ACharnley]

RON thanks for taking the time to write that, it had completely bypassed me the 100K is swinging between +/- 100v relative to ground (duh) so now I understand the parallel statement at 0V. Makes sense. Therefore I accept that from the ADC point of view the resistance is 10K at zero crossing.

There are three conditions that can occur (please correct if I'm wrong):

1. Positive 10V - the PIC ADC samples at a charge rate of 1 -e^-4A
2. Ground - the PIC ADC discharges at ~10k
3. Negative 10V - the PIC ADC discharges through ~9.3K plus 1 -e^-4A.

If I have the explanation correct the measurable impedance is 10K but the source impedance is 100K. We're back to me wondering how the 100K is low enough to charge the ADC in the sampling time available.

Finally the diode would prevent the ADC going below -0.7V but at -0.3V it is damaged.

 

[ACharnley]

I need to do a better job explaining what I'm working with. Here goes.

The power source is a 6 pole dynamo fixed current (saturation point) at around 0.5A, variable voltage as fast as it turns. 0 - 100V is expected. It is a sine wave per say but the magnets don't make it uniform with 3rd and 5th order harmonics. The frequency and voltage are ratio related. For 100V it's 245Hz.

This feeds into an active rectifier. From my previous posts you'll know i've been working on going all N-FET.

First know I must have a measured voltage at "pow" as further fet's will turn on/off to prevent back-flow. At ~8V everything is off (protection mode) and this is where the area of interest comes from - I need to measure 0 to ~8V accurately and shunt the rest off into space.

There are two ways of going about it:

1. look for zero crossing, switch one/other FET.

2. have an "indicator" which AC line is positive (pull a pin up high), keep a track and use the DC reading to turn on the correct FET.

I'd originally went down the measuring and polarity using the duplicate circuits posted in #1. Since I also need the DC voltage at "pow" (which may be slightly different due to diode variance) it made sense to abandon this method. Also worth mentioning, real zero-cross circuits have limitations with wide band voltages (Microchip's built in ZCD can do 6X, i.e 10v to 60v). This is because they use an offset (say 2.5v) and look to see when a series resistor pulls/pushes back to this mark).

I have since been focusing on 2. However, without an enabled FET the ADC will only start seeing a DC voltage at "pow" at 0.7V. I either have to accept being unable to turn the FET's on until this point or use the frequency (which I can work out from the "indicator" pin plus a timer) and some math inside the PIC to calculate the next actual crossing time.

 

[rjenkinsgb]

You cut off the data sheet grab before the other critical line:
Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA

As long as the out-of-range voltage is current-limited it will not cause a problem.
eg. one very crude "zero cross" detect with a PIC is simply a one megohm resistor from mains live to an input. The current is well under 1mA so no harm.

That's the reason for the 1K series resistor after the divider, it means the current from the -0.7V cannot exceed 0.7mA, so safe for the device.


Re. the 100k and timing, it's down to the divider and equivalent resistance.
You are only ever looking at about 1/10th the input voltage swing at the divider junction and the ADC cap.

Think of it as a 10th the input voltage and a 10K series resistor; that's just the same current to the cap so functionally a similar time constant.
The divider effectively reduces the time constant by the division factor as well as the voltage.

 

[ACharnley]

The 20mA is in positive direction, I think in negative it's a lot less. I may be wrong though.

Re: 100k, my understanding is people are saying it doesn't matter what value the resistors are, the same voltage/current will be at the divide. This is where my understanding differs. I assumed the voltage would be the same up to the maximum current draw (limited by the 100k) at which point it would drop, with Microchip saying 10k is the maximum recommended to supply enough current to make the ADC charge.

 

[ronsimpson]

Microchip saying 10k is the maximum recommended to supply enough current to make the ADC charge.

MicroChip thinks you have the input in the range of 0 to 3.3V or 5V. (supply range) The input is in the usable range.
MicroChip ... the ADC needs to push/pull a small amount of current to read. They want a resistor that will drop across it less than one LSB of error. If the ADC is 10 bit that will be 1/000 of the reference voltage. So we are talking 1mV across 10k. Very little current.

You have 100V on 100k or 1mA. You have 1000s of times more current in the 100k than you need to do the conversion.

This example is not quite true ..... I only have 10 different ways to say "you don't have a problem".