This only applies to Timers, CCP values don't increment. If by some rare coincidence writing the low byte first causes a match then it will be cleared lower down before exiting the ISR. I don't know if Oshonsoft will write a 16 bit register or if it will need splitting, depends on the compiler.The only things I can see with his version are:
When reading 16 bit registers one byte at a time, you must read LOW byte first.
When writing them, you must read HIGH byte first.
(The high byte is transferred via a latch to synchronise the two halves).
The conversion (?) has some strange bits like,
Code:
'T1CON=0b00000001; 'timer 1 clocks at
T1CON.7 = 0 '7=RD16 0 = Enables register read/write of Timer1 in two 8-bit operations
T1CON.6 = 1 'T1RUN 1 = Device clock is derived from Timer1 oscillator
T1CON.5 = 1 'T1CKPS.5-4 10 = 1:4 Prescale value
T1CON.4 = 0
T1CON.3 = 1 'T1OSCEN 1 = Timer1 oscillator is enabled
T1CON.2 = 0 'T1SYNC This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
T1CON.1 = 0 'TMR1CS 0 = Internal clock (FOSC/4)
T1CON.0 = 1 'TMR1ON 1 = Enables Timer1
and,
Code:
INTCON.PEIE = 1 '[6]PEIE/GIEL: Peripheral Interrupt Enable bit: When IPEN = 1: 1 = Enables all low-priority peripheral interrupts
INTCON.GIE = 1 '[7]GIE/GIEH: Global Interrupt Enable bit: When IPEN = 1:1 = Enables all low-priority peripheral interrupts
Enable High 'This is set for SERVOS
Enable Low 'This is set for GPS later
I also note that your code enables interrupt priority.
Mike.
Edit, the CCP1CON value is wrong too.
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