Mosfets drain (n type the tab on to-220 mosfets)

1. Everything made of copper - including any connections between pads and mounting holes with copper around and/or through plated - must be made using Top, Bottom or Multi Layer pads, whether round, oval, rectangular or polygons and editing the points;
2. Holes without copper should be made using the Hole tool or Solid region set as Board Cutout;
3. All pads should be numbered but different pads can have the same number. For example, for a TO-220 packaged power transistor which has 3 pins on the symbol (CBE or DGS) but has 4 electrical connections to the pins and the tab that need to be mapped onto 4 pads so two of the pads can have the same number assigned to them;
4. All pads that are connected together by copper (see (1) above) must have the same number;
5. Do not try to use vias in a PCB footprint. Use a multilayer pad set to the same dimensions as a via (for more on this, see: https://easyeda.com/forum/topic/How...CB-footprint-a34cf68d58414138898a56de60abd8c1);
6. Because they cannot be assigned pad numbers, the following elements of Tracks, Arcs, or Solid Regions should only be used to create copper elements in PCB Footprints if they are selected after placement, right-clicked on and then Converted to Pads;
7. Because they cannot be assigned pad numbers and cannot be converted to pads, the following elements of Rectangles, Circles, Text or imported images should not be used in the construction of copper elements in a PCB Footprint. If a PCB Footprint containing such elements is then placed on a PCB, wherever a track or copper area crosses or passes too close to any of these elements, it will generate DRC errors. The only exception to this is when such elements are placed within and completely surrounded by a pad so that they cannot be connected to. An example of this is shown in: https://easyeda.com/andyfierman/avoiding-drc-errors-in-footprints;
8. Do not assign Nets to any part of a PCB Footprint: they will generate DRC errors because there is no guarantee that a net with the same name as that assigned to a pad in the Footprint, will be connected to that pad by everyone who uses that Footprint. For example, what one user may call GND in a PCB Footprint, may be connected by another user, to a net in the PCB called GRND, Earth, 0V or something entirely different like VSS;
9. As described in (3) above, the Schematic Symbol for a device may have fewer pins than the number of electrical connections to the physical package. For example, discrete MOSFETs usually have only a gate, source and drain connection but many are packaged so that although there is a Gate is connected to a single pad, the Source may be connected to 3 pads, which are all directly shorted together on or within the package and the Drain to 4 pads. To avoid over complicating the Schematic Symbol - and therefore cluttering up the Schematic - this is easily and most effectively handled by mapping each pin on the Schematic Symbol onto one or more pads, assigned the same number, on the PCB Footprint;
10. A PCB Footprint must not have fewer pads than the number of pins on the device that is to be placed on it. Do not omit pads for unconnected or NC pins on the device: they are often required for mechanical or thermal stability. This must include things like, for example, ground and shield pins on USB and Ethernet connectors.

For The Popcorn said:

Here is a revised footprint that does work. No DRC errors or other issues.

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ChrisP58 said:

There will be a lot of heat conducted by the bolt, but if you're adding vias, they should be placed where they will do the most good.

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MrDEB said:

Will recheck my layout as per post 127.

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• In post 109, I made a custom footprint for you that I thought would work.
• In post 114, you tried it and it did not work properly. My apologies.
• In post 121, I posted a revised footprint that I had tested in an actual circuit, and posted pictures documenting it did work. This took a couple hours to find the proper method to build a multilayer footprint.
• In post 128, you said my footprint didn't work but this wasn't the REVISED FOOTPRINT from post 121; it was the original footprint from post 109. Despite the warnings I had posted between post 109 – 121 not to use it.
• In post 131, you finally say you downloaded the new footprint from post 121. After you had claimed that it didn't work in post 128.[/B]

For The Popcorn said:

Not that I give a rat's a$$, but I don't think your board is going to work very well. I don't think I'd run three traces between the pads on 1206 resistors (and there are many places where clearance is really tight where's there's no need) but that's not the fatal flaw.......

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